Process for manufacturing a byte selection transistor for a matrix of non volatile memory cells and corresponding structure

ABSTRACT

A process for manufacturing a byte selection transistor for a matrix of non volatile memory cells organised in rows and columns integrated on a semiconductor substrate, each memory cell comprising a floating gate transistor and a selection transistor, the process providing the following steps: defining on a same semiconductor substrate respective active areas for the byte selection transistor, for the floating gate transistor and for the selection transistor split by portions of insulating layer; depositing a multilayer structure comprising at least a gate oxide layer, a first polysilicon layer, a dielectric layer on the whole substrate and a second polysilicon layer, characterised in that it comprises the following steps: removing through a traditional photolithographic technique the multilayer structure to form at least a couple of two bands developing substantially in a parallel way to the columns of the matrix of memory cells, the first band being effective to define the gate regions of the byte selection transistor and of the selection transistor, the second band being effective to define the gate region of the floating gate transistor, a portion of the first band further extending on the portion of insulating layer which is adjacent to the byte selection transistor, forming an opening in the portion up to expose the first polysilicon layer, forming a conductive layer in the opening to put said first polysilicon layer in electric contact with said second polysilicon layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a process for manufacturing a byteselection transistor for a matrix of non volatile memory cells andcorresponding structure.

More specifically, the invention relates to a process for manufacturinga byte selection transistor for a matrix of non volatile memory cellsorganised in rows and columns integrated on a semiconductor substrate,each memory cell comprising a floating gate transistor and a selectiontransistor, the process providing the following steps:

defining on a same semiconductor substrate respective active areas forsaid byte selection transistor, for said floating gate transistor andfor said selection transistor split by portions of insulating layer;

depositing a multilayer structure comprising at least a gate oxidelayer, a first polysilicon layer, a dielectric layer on the wholesubstrate and a second polysilicon layer.

The invention relates also to a circuit structure comprising a matrix ofnon volatile memory cells organised in rows and columns integrated on asemiconductor substrate, associated to a circuitry comprising high andlow voltage transistors, each memory cell comprising a floating gatetransistor and a selection transistor, said rows being interrupted by atleast a couple of byte selection transistors, said transistors beingmanufactured in respective active areas delimited by portions ofinsulating layer.

The invention relates particularly, but not exclusively, to a processfor manufacturing a byte selection transistor for a matrix of nonvolatile memory cells and the following description is made withreference to this field of application for convenience of illustrationonly.

2. Description of the Related Art

As it is well known, a matrix of non volatile memory cells comprises aplurality of non volatile memory cells integrated on a semiconductormaterial substrate arranged in rows and columns.

Each non volatile cell is formed by a floating gate transistor and by aselection transistor. The floating gate region of the floating gatetransistor is formed on a semiconductor substrate and split therefrom bya thin gate oxide layer. A control gate region is capacitively coupledto the floating gate region by means of a dielectric layer and metallicelectrodes are provided to contact the drain, source terminals and thecontrol gate region in order to apply predetermined voltage values tothe memory cell. The selection transistor is instead manufactured bymeans of a traditional MOS transistor comprising a gate region formed ona semiconductor substrate and split therefrom by a thin gate oxidelayer. Source and drain regions are integrated in the substrate at thegate region ends.

The cells belonging to a same word line have a common electric linedriving the respective control gates by means of the byte selectiontransistor, while the cells belonging to a same bit line have commondrain terminals.

The matrix of memory cells is organized in turn in bytes, each onecomprising 8 bits (or multiples). Each byte can be selected from outsidethe matrix by means of a byte transistor located in correspondence witheach byte.

A first known technical solution to form a matrix of non volatile cellsprovides the use of two different masks for manufacturing the selectionand byte transistors having a gate region with a single polysiliconlevel, while the gate region of the floating gate transistor ismanufactured with a double polysilicon layer.

Therefore, in the matrix portion wherein the selection and bytetransistors are manufactured a removal step of one of the twopolysilicon layers used to form the double polysilicon layer must beperformed.

Although advantageous under many aspects, this first solution hasseveral drawbacks. In fact, the removal step of a polysilicon layer fromthe active areas of the selection and byte transistors of one of the twopolysilicon layers can degrade the electric features of these devices.Moreover the resulting structure comprises the series of devices withdifferent heights which make the cleaning steps provided in thetraditional process flow particularly difficult.

SUMMARY OF THE INVENTION

According to principles of the present invention a process is describedfor manufacturing a byte transistor integrated in a matrix of nonvolatile memory cells, having such structural and functional features asto allow the number of masks to be used in the manufacturing process tobe reduced overcoming the limits and/or drawbacks still affecting priorart devices.

The solution idea underlying the present invention is to form the gateregion of the byte selection transistor using the same two overlappedlayers which are used for the gate regions of the selection transistorand for the gate regions of the floating gate transistor and to form theelectric connection between these two polysilicon layers near the bytetransistor.

The features and advantages of the device according to the inventionwill be apparent from the following description of an embodiment thereofgiven by way of non-limiting example with reference to the attacheddrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

In these drawings:

FIG. 1 shows a simplified diagram of a wiring diagram of a matrix of nonvolatile memory cells comprising bit and byte selection transistors;

FIG. 2 shows a magnification of a portion A of the matrix of cells ofFIG. 1 comprising a byte selection transistor according to theinvention;

FIG. 3 is a sectional view along the line I-I of FIG. 2 of a traditionalmemory cell;

FIGS. 4 and 5 are sectional views along the line II-II of a matrixportion of FIG. 2 during the two different steps of the manufacturingprocess.

DETAILED DESCRIPTION OF THE INVENTION

With reference to these drawings, a process for manufacturing a byteselection transistor for a matrix of non volatile memory cells isdescribed.

The present invention can be implemented together with other integratedcircuit manufacturing techniques presently used and well known in thisfield, therefore only those commonly used process steps which arenecessary to understand the present invention are included together withthe description of the invention.

The figures representing cross sections of integrated circuit portionsduring the manufacturing are not drawn to scale, but they are insteaddrawn in order to show the most important features of the invention.

With reference to FIGS. 1-3, a thick oxide layer 2 is selectivelyformed, for example grown, on a semiconductor substrate in order to formactive areas 3 wherein the non volatile memory cells 5 are respectivelyformed, each one comprising a floating gate transistor 6 and a selectiontransistor 7 and byte selection transistors 8. The oxide layer 2 canalso be a trench or other isolation structure.

As shown in FIG. 3, a second oxide layer 9 of a first thickness to formthe gate oxides of the floating gate transistor 6, of the selectiontransistor 7 and of the byte selection transistor 8. In someembodiments, a third oxide layer 10 of a second thickness being lessthan the thickness of the second layer 9 to form the tunnel oxide of thefloating gate transistor 6 are selectively formed.

Traditionally, in this process step the gate oxide layer of high voltagetransistors comprised in the matrix control circuitry, not shown in thedrawings, is also formed by means of the second oxide layer 9.

A layered structure is then formed on the whole substrate 1 comprising afirst polysilicon layer 11, a fourth dielectric layer 12 calledinterpoly oxide and a second polysilicon layer 13.

This fourth dielectric layer 12 is for example an ONO(Oxide-Nitride-Oxide) layer.

Advantageously, in this process step after depositing the fourthdielectric layer 12 called interpoly oxide a fifth oxide layer is alsoformed, to form the gate oxide layer of low voltage transistors whichcan be used to manufacture other types of memory devices on the samesubstrate 1, such as for example ROM or SDRAM memories, and the devicesimplementing the matrix control logic, non shown in the drawings.

Advantageously, by forming this fifth oxide layer last, the devicesimplementing the low voltage control logic are manufactured with amanufacturing process not depending on the process used for the memorymatrix and high voltage devices. It is thus possible to perform anoptimisation of manufacturing process parameters of single devices.

This layered structure is selectively removed, as shown in FIG. 2, bymeans of a photolithographic process providing the use of a mask called“of the self-aligned etching”, to form simultaneously the gate regionsof the floating gate transistor 6, of the selection transistor 7 and ofthe byte selection transistor 8.

Two bands S1 and S2 are thus formed on the substrate 1. The band S1 incorrespondence with the respective active areas 3 of the selectiontransistor 7 and of the byte selection transistor 8 forms the respectivegate regions thereof, while the band S2 in correspondence with therespective active areas 3 of the floating gate transistor 6 forms therespective gate regions thereof.

According to the invention, the band S1 extends over the byte transistor8 on the oxide layer 2 in order to form a pad 4.

This pad 4 is used to put the first polysilicon layer 11 in contact withthe second polysilicon layer 13.

Advantageously, the width WI of the pad 4 is greater than the width W2of the portion S1 which forms the gate regions of transistors 7 and 8.

In other words, the band S1 has an enlarged portion between adjacentbyte selection transistors.

In particular, as shown in greater detail in FIGS. 4 and 5, according tothe invention an opening 4 a exposing the dielectric layer 12 is formedin the second polysilicon layer 13 having a width W3 within said pad 4.

This dielectric layer 12 is then removed through the opening 4 a formedin the second polysilicon layer 13.

Advantageously, this opening 4 a is formed in the same process step inwhich the gate regions of transistors of the low voltage circuitryassociated to the matrix are manufactured.

At this point the process continues with the dopant implantation stepsprovided by the traditional process flow to form the junctions of matrixtransistors.

Advantageously, the process then continues with the formation of a metallayer 14 on the whole substrate 1 surface. A thermal treatment is thenperformed to let the metal layer react with the substrate 1 surface andwith the polysilicon layers 11 and 13 which are not covered bydielectric to form a silicide layer.

During the thermal treatment the transition metal only reacts with thatsubstrate 1 portion not comprising an oxide layer. Therefore the secondpolysilicon layer 13 and the portion of the first polysilicon layer 11exposed through the opening 4 a are thus covered by a low resistancelayer.

The interconnection lines used in the matrix of cells are formed at thisstage. In particular, a conductive layer 15 is formed in the opening 4 aformed in the second polysilicon layer 13 in order to fill at leastpartially said opening 4 a. The conductive layer 15 puts the firstpolysilicon layer 11 in electrical contact with the second polysiliconlayer 13, as shown in FIG. 5.

Advantageously, a portion 15 a of the conductive layer 15 can be formedin other to locations, for example, to put a junction of the byteselection transistor 8 in contact with the gate region of the floatinggate transistor 6 of the memory cell 5.

The conductive layer 15 can be a further polysilicon layer or ametallization layer.

The circuit structure according to the invention is now described,comprising a matrix of non volatile memory cells, for example of theEEPROM type. This matrix comprises a plurality of non volatile memorycells 5 integrated on a semiconductor material substrate 1 arranged inrows, or word lines W, . . . , WLn, WLn+1 and columns or bit lines B0, .. . , BL7, as shown in FIG. 1. Traditionally, a dummy reference columnBL is between two adjacent bytes.

Each non volatile cell 5 is formed by a floating gate transistor 6 andby a selection transistor 7. The floating gate region of the floatinggate transistor 6 is formed on a semiconductor substrate 1 and splittherefrom by means of a gate oxide layer 9. A control gate region iscapacitively coupled to the floating gate region by means of adielectric layer and metallic electrodes are provided to contact thedrain, source terminals and the control gate region, for example CGn,GCn+1, in order to apply predetermined voltage values to the memorycell.

The cells 5 belonging to a same word line have a common electric linedriving the respective control gate regions by means of the byteselection transistor 7, while the cells 5 belonging to a same bit linehave common drain terminals.

Also the control circuitry of the matrix of memory cells traditionallycomprising high voltage transistors to handle the signals in the matrixof memory cells is integrated on the same substrate 1.

The matrix of memory cells is organized in turn in bytes B, each onecomprising 8 bits (or multiples). Each byte can be selected from outsidethe matrix by means of a byte selection transistor 8 located incorrespondence with each byte. Each byte selection transistor 8 isformed in a corresponding active area 3 delimited by a thick oxide layer2.

According to the invention, the gate regions of floating gatetransistors, of selection transistors and of byte selection transistorsare formed by means of a muitilayer structure formed on thesemiconductor substrate 1 comprising a first oxide layer 9, a firstpolysilicon layer 11, a second oxide layer 12 and a second polysiliconlayer 13. In particular, this multilayer structure comprises a firstband S1 common to all selection transistors 7 belonging to the same byteand to the relevant byte selection transistor 8 and a second band S2common to all floating gate transistor 6 belonging to the same byte. Aportion 4 of this band S1 also extends on the thick oxide layer 2delimiting the active area 3 of the byte selection transistor 8.

In particular, the band S1 in correspondence with the respective activeareas 3 of the selection transistor 7 and of the byte selectiontransistor 8 forms the respective gate regions thereof, while the bandS2 in correspondence with the respective active areas 3 of the floatinggate transistor 6 forms the respective gate regions thereof.

Advantageously, the portion 4 can have a higher amplitude than theportion of the band S1 forming the gate regions of selection transistorsand of the byte selection transistors in correspondence with the activeareas 3 of these transistors 7, 8. In fact this portion 4 can have thepad 4 shape.

The second dielectric layer 12 and the second polysilicon layer 13 areprovided with an opening 4 a in correspondence with this pad 4.Advantageously, the second polysilicon layer 13 and the portion of thefirst polysilicon layer 11 exposed through the opening 4 a is covered bya low resistivity layer such as for example a silicide layer.

According to the invention, a conductive layer 15 fills at leastpartially the opening 4 a forming the electric connection between thefirst and second polysilicon layers.

In conclusion, with the process according to the invention aparticularly compact circuit structure is obtained, since the pad 4,which is used to put the two polysilicon layers forming the gate regionsof selection transistors 7, 8 in electric contact and thus ensure thecorrect operation of these devices, is formed between two byte selectiontransistors 8 belonging to two adjacent bytes. The distance providedbetween two adjacent byte selection transistors 8 is selected in orderto reduce the formation of parasite transistors between these twoadjacent transistors which have to handle high voltages.

The further advantage of the present invention is to manufacturetransistors in the matrix with a same number of polysilicon layers inorder to facilitate the etching and selective removal steps beingnecessary during the manufacturing process steps. Forming all gateregions in the same process step considerably improves the reliabilityof the so-formed devices.

Advantageously, the circuit structure according to the invention allowsvery compact devices to be manufactured, such as for example SmartCardproducts, or devices which can be used in mobile telephony applicationswhich must have a low voltage interface with the outside. Traditionally,the driving of the memory matrix in the circuit structure according tothe invention is instead handled by high voltage transistors.

All of the above U.S. patents, U.S. patent application publications,U.S. patent applications, foreign patents, foreign patent applicationsand non-patent publications referred to in this specification and/orlisted in the Application Data Sheet, are incorporated herein byreference, in their entirety.

From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the invention. Accordingly, the invention is notlimited except as by the appended claims.

1. A process for manufacturing a byte selection transistor for a matrixof non volatile memory cells organised in rows and columns integrated ona semiconductor substrate, each memory cell comprising a floating gatetransistor and a selection transistor, the process providing thefollowing steps: defining on a semiconductor substrate one or moreactive areas for said byte selection transistor, for said floating gatetransistor and for said selection transistor, the active areas havingportions of an insulating layer adjacent thereto; depositing amultilayer structure comprising at least a gate oxide layer, a firstpolysilicon layer, a dielectric layer and a second polysilicon layer;removing through a photolithographic technique said multilayer structureto form at least two bands, the first band being effective to define thegate regions of said byte selection transistor and of said selectiontransistor, the second band being effective to define the gate region ofsaid floating gate transistor, a portion of said first band furtherextending on the portion of insulating layer which is adjacent to saidbyte selection transistor, forming an opening in said portion to exposesaid first polysilicon layer, forming a conductive layer in said openingto put said first polysilicon layer in electrical contact with saidsecond polysilicon layer.
 2. The process for manufacturing a byteselection transistor according to claim 1 wherein said portion thatextends over the insulating layer has a greater width than the width ofthe gate regions of single transistors.
 3. The process for manufacturinga byte selection transistor according to claim 1 wherein said conductivelayer is a polysilicon layer.
 4. The process for manufacturing a byteselection transistor according to claim 1 wherein said conductive layeris a metallization layer.
 5. The process for manufacturing a byteselection transistor according to claim 1, including: forming a silicidelayer on said second polysilicon layer and on the portion of said firstpolysilicon layer exposed through said opening.
 6. A circuit structurecomprising: a semiconductor substrate; and a matrix of non volatilememory cells organised in rows and columns integrated on a semiconductorsubstrate, the substrate having thereon circuitry comprising high andlow voltage transistors, each memory cell comprising a floating gatetransistor and a selection transistor, said rows being interrupted by atleast a couple of byte selection transistors, said transistors beingmanufactured in respective active areas delimited by portions of aninsulating layer, said circuit structure having a first and a secondmultilayer band formed on said semiconductor substrate, each band havinga first gate oxide layer, a first polysilicon layer, a second dielectriclayer and a second polysilicon layer, said first band defining the gateregions of said byte selection transistor and of said selectiontransistor in correspondence with said respective active areas andhaving a portion extending on a portion of the insulating layer adjacentto said byte selection transistor, said second band defining the gateregions of said floating gate transistor, said portion being providedwith an opening, formed in said second dielectric layer and in saidsecond polysilicon layer, filled at least partially by a conductivelayer.
 7. The circuit structure according to claim 6 wherein saidportion has a greater width at the location of said opening than thewidth at the location of said active areas.
 8. The circuit structureaccording to claim 6, characterised in that said conductive layer is apolysilicon layer.
 9. The circuit structure according to claim 6 whereinsaid conductive layer is a metallization layer.